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Ordering number : EN4677
CMOS LSI
LC66354B, 66356B, 66358B
Four-bit Single-Chip Microcontrollers On-Chip 4 K/6 K/8 K-byte ROM
Overview
The LC66354B, LC66356B and LC66358B are 42-pin package four-bit CMOS microcontrollers that integrate on a single chip all functions required in a control microcontroller, including ROM, RAM, I/O ports, serial interfaces, comparator inputs, three-value inputs, timers and an interrupt system. These products differ from the earlier LC66358A series in their power supply voltage range and operating speed specifications.
*
Features and Functions
* ROM (with 4 K-, 6 K- and 8 K-byte capacities) and RAM (512 4-bit digits) on chip * LC66000 series compatible instruction set (128 instructions) * A total of 36 I/O port pins * Two eight-bit serial interfaces that can be connected in cascade to form a 16-bit interface * Instruction cycle time: 0.92 to 10 s (3 to 5.5 V) The earlier LC66358A series had instruction cycle times of from 1.96 to 10 s (at 3 to 5.5 V) and from 3.92 to 10 s (at 2.2 to 5.5 V). * Powerful timer and prescaler functions *
* * * * *
Time limit timer, event counter, pulse width measurement and square wave output using a 12-bit timer. Time limit timer, event counter, PWM output and square wave output using an 8-bit timer. Time base function using a 12-bit prescaler. Powerful interrupt system with eight interrupts and eight vector locations External interrupts: three interrupts and three vector locations Internal interrupts: five interrupts and five vector locations Flexible I/O functions Comparator inputs, three-value inputs, 20 mA drive outputs, 15 V withstand voltage, pull-up or open-drain option switching Runaway detection function (watchdog timer) option Eight-bit I/O function Power reduction functions using halt and hold modes Packages: DIP42S, QIP48E (QFP48E) Evaluation LSI: used together -- LC66599 (evaluation chip) + EVA850/800TB6630X -- LC66E308 (on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
93098HA (OT) / 83194TH (OT) B8-0696 No. 4677-1/23
LC66354B, 66356B, 66358B
Series Structure
Product name LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S* LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B* LC66562B/566B LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 Note: * Under development Pins 42, 48 42, 48 64 42, 48 44 64 42, 48 64 64 42, 48 42, 48 42, 48 42, 48 64 64 ROM capacity 4 K/6 K/8 K bytes 4 K/6 K/8 K bytes 6 K/8 K/12 K/16 K bytes 4 K/6 K/8 K bytes 4 K/6 K/8 K bytes 6 K/8 K/12 K/16 K bytes 4 K/6 K/8 K bytes 6 K/8 K bytes 12 K/16 K bytes EPROM, 8 K bytes OTPROM, 8 K bytes EPROM, 8 K bytes OTPROM, 8 K bytes EPROM 16 K bytes OTPROM 16 K bytes RAM capacity 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W DIP64S DIP42S DIP64S DIP64S DIC42S (window) DIP42S DIC42S (window) DIP42S DIC64S (window) DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP64E QFC48 (window) QFP48E QFC48 (window) QFP48E QFC64 (window) QFP64E Evaluation window and OTP versions 4.5 to 5.5 V/0.92 s Low-voltage, high-speed version 3.0 to 5.5 V/0.92 s Low-voltage version 2.2 to 5.5 V/3.92 s Normal version 4.0 to 6.0 V/0.92 s Features
Pin Assignments
Top view
We recommend using reflow soldering methods to mount the QFP package version. Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is immersed in a solder bath (solder dip or spray techniques) are used.
No. 4677-2/23
LC66354B, 66356B, 66358B System Block Diagram
Differences between the LC66354B, LC66356B and LC66358B and the LC6630X Series
Parameter System Differences * Hardware wait time (number of cycles) when HOLD mode is cleared LC6630X series (including the LC66599 evaluation chip) 65536 cycles At 4 MHz (Tcyc = 1 s): About 64 ms LC6635XB series 16384 cycles At 4 MHz (Tcyc = 1 s): About 16 ms The value FFC is loaded. 3.0 to 5.5 V/0.92 to 10 s LC6635XA, 2.2 to 5.5 V/3.92 to 10 s, 3.0 to 5.5 V/1.96 to 10 s
* Value of timer 0 on reset The value FFO is loaded. (including the value after HOLD mode is cleared) LC66304A, 66306A, 66308A Main differences in product characteristics 4.0 to 6.0 V/0.92 to 10 s * Operating power supply voltage/operating speed LC66E308, 66P308 (cycle time) 4.5 to 5.5 V/0.92 to 10 s
Note: 1. An RC oscillator cannot be used with the LC66354B, LC66356B and LC66358B. 2. In addition, there are differences in the output currents, comparator input voltages and other aspects. For details, refer to the individual catalogs for the LC66308A, LC66E308 and the LC66P308. 3. These points require care when using the LC66E308 or LC66P308 for evaluation purposes.
Package Dimensions
unit: mm 3025B-DIP42S
[LC66354B, 66356B, 66358B]
unit: mm 3156-QFP48E
[LC66354B, 66356B, 66358B]
SANYO: DIP42S SANYO: QFP48E No. 4677-3/23
LC66354B, 66356B, 66358B Pin Function Overview
Pin I/O Overview I/O ports P00 to P03 I/O * Input or output in 4-bit or 1-bit units * P00 to P03 have control functions in HALT mode. Output drive type Option Value on reset
P00 P01 P02 P03
* P-channel: pull-up MOS type * N-channel: intermediate sink current type
* Either with pull-up MOS or n-channel OD output * Reset output level
High or low level (option)
P10 P11 P12 P13
I/O
I/O ports P10 to P13 * Input or output in 4-bit or 1-bit units
* P-channel: pull-up MOS type * N-channel: intermediate sink current type
* Either with pull-up MOS or n-channel OD output * Reset output level
High or low level (option)
I/O ports P20 to P23 * Input or output in 4-bit or 1-bit units * P20 is also used as the serial input SI0 pin. P20/SI0 P21/SO0 P22/SCK0 P23/INT0 * P21 is also used as the serial output SO0 pin. * P22 is also used as the serial clock SCK0 pin. * P23 is also used as the INT0 interrupt request, the timer 0 event counter and pulse width measurement input. I/O ports P30 to P32 * Input or output in 3-bit or 1-bit units P30/INT1 P31/POUT0 P32/POUT1 * P30 is also used as the INT1 interrupt request. I/O * P31 is also used for square wave output from timer 0. * P32 is also used for square wave output from timer 1 and PWM output. * P-channel: CMOS type * N-channel: intermediate sink current type (+15 V withstand voltage in OD) * Either CMOS or n-channel OD output H * P-channel: CMOS type * N-channel: intermediate sink current type (+15 V withstand voltage in OD) * Either CMOS or n-channel OD output H
I/O
Hold mode control input * Hold mode is entered if a HOLD instruction is executed when HOLD is low. * When in hold mode, the CPU is reactivated by setting HOLD to the high level. P33/HOLD I * P33 can also be used as an input port along with P30 to P32. * When P33/HOLD is low, the CPU will not be reset by a low level on RES. Therefore, RES cannot be used in applications that set P33/HOLD low when power is first applied.
I/O ports P40 to P43 P40 P41 P42 P43 * Input or output in 3-bit or 1-bit units I/O * I/O in 8-bit units when used in conjunction with P50 to P53 * Output of 8-bit ROM data when used in conjunction with P50 to P53 * P-channel: pull-up MOS type * N-channel: intermediate sink current type (+15 V withstand voltage in OD) * Either with pull-up MOS or n-channel OD output
H
Continued on next page. No. 4677-4/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Pin I/O Overview I/O ports P50 to P53 * Input or output in 4-bit or 1-bit units P50 P51 P52 P53/INT2 * I/O in 8-bit units when used in conjunction with P40 to P43 * Output of 8-bit ROM data when used in conjunction with P40 to P43 * P53 is also used for the INT2 interrupt request. I/O ports P60 to P63 * Input or output in 4-bit or 1-bit units P60/SI1 P61/SO1 P62/SCK1 P63/PIN1 * P60 is also used as the serial input SI1 pin. I/O * P61 is also used as the serial output SO1 pin. * P62 is also used as the serial clock SCK1 pin. * P63 is also used as the timer 1 event counter input. * P-channel: CMOS type * N-channel: intermediate sink current type (+15 V withstand voltage in OD) * Either CMOS or n-channel OD output H * P-channel: pull-up MOS type * N-channel: intermediate sink current type (+15 V withstand voltage in OD) Output drive type Option Value on reset
I/O
* Either with pull-up MOS or n-channel OD output
H
I/O ports PC2 and PC3 * Output in 4-bit or 1-bit units PC2/VREF0 PC3/VREF1 I/O * PC2 is also used as the VREF0 comparator comparison voltage pin. * PC3 is also used as the VREF1 comparator comparison voltage pin. * P-channel: CMOS type * N-channel: intermediate sink current type * Either CMOS or n-channel OD output
H
Dedicated input ports PD0 to PD3 * Can be switched to use as comparator inputs under program control. PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3 The PD0 comparison voltage is VREF0. The PD1 to PD3 comparison voltage is VREF1. Comparisons can be specified in units of PD0, PD2, and PD2 and PD3 together. PE0/TRA PE1/TRB Dedicated input ports I * Can be switched to function as threevalue inputs under program control. System clock oscillator external connection When an external clock is used, leave OSC2 open and input the clock signal to OSC1. System reset input RES I The CPU is initialized if a low level is input to RES when the P33/HOLD pin is high. CPU test pin TEST I This pin must be connected to VSS during normal operation. Power supply connections Normal input
I
Normal input
OSC1 OSC2
I O
* Selection of either ceramic oscillator or external clock input.
VDD VSS
Note: Pull-up MOS output:........A pull-up MOS transistor is connected to the output circuit. CMOS output: .................Complementary output OD output:.......................Open drain output
No. 4677-5/23
LC66354B, 66356B, 66358B User Option Types 1. Port 0 and 1 reset time output level option The output levels of ports 0 and 1 can be selected from the following two options in 4-bit units.
Option High level output at reset time Low level output at reset time Conditions and notes Ports 0 and/or 1 in 4-bit sets Ports 0 and/or 1 in 4-bit sets
2. Oscillator circuit option
Option Circuit Conditions and notes
External clock
This input is a Schmitt specification input.
Ceramic oscillator
Note: There is no RC oscillator option.
3. Watchdog timer option The presence or absence of a watchdog timer can be selected as an option. 4. Port output type option * One of the following two output circuit options can be selected for each bit in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5. P6 and PC.
Option Circuit Conditions and notes
Open drain output
P2, P3, P5 and P6 are Schmitt inputs.
P2, P3, P5 and P6 are Schmitt inputs. Built-in pull-up resistor output CMOS outputs (P2, P3, P6 and PC) and pull-up MOS outputs (P0, P1, P4 and P5) are differentiated according to the drive capacity of the p-channel transistor.
* The PD comparator inputs and the PE three-value inputs are selected in software.
No. 4677-6/23
LC66354B, 66356B, 66358B
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN (1) VIN (2) VOUT (1) VOUT (2) ION Output current per pin -IOP (1) -IOP (2) ION (1) Total pin current ION (2) IOP (1) IOP (2) Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD P2, P3 (except for the P33/HOLD pin), P4, P5, P6 Other inputs P2, P3 (except for the P33/HOLD pin), P4, P5, P6 Other outputs P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, PC P0, P1, P4, P5 P2, P3 (except for the P33/HOLD pin), P6, PC P0, P1, P2, P3, (except for the P33/HOLD pin), P40, P41 P5, P6, P42, P43, PC P0, P1, P2, P3 (except for the P33/HOLD pin), P40, P41 P5, P6, P42, P43, PC Ta = -30 to +70C DIP42S QFP48E Applicable pins, notes Conditions Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to VDD + 0.3 20 2 4 75 75 25 25 600 430 -30 to +70 -55 to +125 Unit V V V V V mA mA mA mA mA mA mA mW mW C C 5 1 2 1 2 3 4 4 3 3 4 4 Note
Output voltage
Note: 1. Applies to open drain output specification pins. The rating from the "other pin" entry applies for specifications other than the open drain output specification. 2. Levels up to the free-running oscillation level are allowed for the oscillator input and output pins. 3. Inflow current 4. Outflow current (Applies to the pull-up output specification and CMOS output specification pins.) 5. We recommend using reflow soldering methods to mount the QFP package version. Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is immersed in a solder bath (solder dip or spray techniques) are used.
Allowable Operating Ranges at Ta = -30 to + 70C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified
Parameter Operating supply voltage Memory hold supply voltage Symbol VDD VDD (H) VIH (1) VDD VDD P2, P3 (except for the P33/HOLD pin), P4, P5, P6 P33/HOLD, RES, OSC1 P0, P1, PC, PD, PE PE PE PD0, PC2 PD1, PD2, PD3, PC3 P2, P3 (except for the P33/HOLD pin), P5, P6, RES, OSC1 P33/HOLD P0, P1, P4, PC, PD, PE, TEST PE Applicable pins Conditions 0.92 Tcyc 10 s In HOLD mode With the output n-channel transistor off With the output n-channel transistor off With the output n-channel transistor off Using three-value input Using three-value input Using comparator input With the output n-channel transistor off VDD = 1.8 to 5.5 V With the output n-channel transistor off Using comparator input VSS VSS 0.4 (10) Ratings min 3.0 1.8 0.8 VDD typ max 5.5 5.5 13.5 Unit V V V 1 Note
Input high level Voltage
VIH (2) VIH (3) VIH (4)
0.8 VDD 0.75 VDD 0.8 VDD 0.4 VDD 1.5 VSS
VDD VDD VDD 0.6 VDD VDD VDD - 1.5 0.2 VDD 0.2 VDD 0.25 VDD 0.2 VDD 4.35 (0.92)
V V V V V V V V V V MHz (s)
2 3
Middle level input voltage Common mode input voltage range
VIM VCMM (1) VCMM (2) VIL (1)
1
Input low level voltage
VIL (2) VIL (3) VIL (4)
3
Operating frequency (instruction cycle time)
fOP (TCYC)
Note: 1. Applies to open drain specification pins. However, the rating for VIH (2) applies to the P33/HOLD pin. Ports P2, P3 and P6 cannot be used as input pins when CMOS output specifications are used. 2. Applies to open drain specification pins. 3. When PE is used as a three-value input, VIH (4), VIM and VIL (4) apply. Port P3 cannot be used as input pins when CMOS output specifications are used.
Continued on next page. No. 4677-7/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Ratings min typ max
Parameter
Symbol
Applicable pins
Conditions See Figure 1. With the signal input to OSC1 and with OSC2 open (with external clock input selected for the oscillator circuit option) See Figure 1. With the signal input to OSC1 and with OSC2 open (with external clock input selected for the oscillator circuit option) See Figure 1. With the signal input to OSC1 and with OSC2 open (with external clock input selected for the oscillator circuit option)
Unit
Note
Frequency
fext
0.4
4.35
MHz
External clock input conditions
Pulse width
textH textL
OSC1
100
ns
Rise/fall times
textR textF
30
ns
Electrical Characteristics at Ta = -30 to + 70C, VSS = 0 V, VDD = 3.5 to 5.5 V unless otherwise specified
Parameter Symbol Applicable pins P2, P3 (except for the P33/HOLD pin), P4, P5, P6 P0, P1, PC, OSC1, RES, P33/HOLD Conditions VIN = 13.5, With the output n-channel transistor off VIN = VDD, With the output n-channel transistor off VIN = VDD, With the output n-channel transistor off -1.0 Ratings min typ max 5.0 Unit Note
IIH (1)
A
1
Input high level current
IIH (2)
1.0
A
1
IIH (3)
PD, PE, PC2, PC3
1.0
A
1
IIL (1) Input low level current IIL (2)
V = VSS, Inputs other than PD, PE, IN With the output n-channel PC2 and PC3 transistor off PC2, PC3, PD, PE P2, P3 (except for the P33/HOLD pin) P6, PC P0, P1, P4, P5 P0, P1, P4, P5 P0, P1, P2, P3, P4, P5, P6, PC (except for the P33/HOLD pin) P0, P1, P2, P3, P4, P5, P6, PC (except for the P33/HOLD pin) P2, P3, P4, P5, P6 P0, P1, PC PD1, PD2, PD3 PD0 VIN = VSS, With the output n-channel transistor off IOH = -1 mA IOH = -0.1 mA IOH = -50 A IOH = -30 A VIN = VSS, VDD = 5.5 V IOL = 1.6 mA
A
2
-1.0 VDD - 1.0 VDD - 0.5 VDD - 1.0 VDD - 0.5 -1.6 0.4
A
2
VOH (1) Output high level voltage VOH (2) Output pull-up current IPO VOL (1) Output low level voltage VOL (2) IOFF (1) IOFF (2) VOFF (1) VOFF (2) VHIS
V
3
V mA V
4 4 5
IOL = 8 mA VIN = 13.5 V VIN = VDD VIN = VSS to VDD - 1.5 V VIN = 1.5 to VDD 50 50 0.1 VDD
1.5 5.0 1.0 300 300
V A A mV mV V 5 5
Output off leakage current
Comparator offset voltage Hysteresis voltage Schmitt characteristics High level thresHOLD voltage Low level thresHOLD voltage
VtH
P2, P3, P5, P6, OSC1 (EXT), RES
0.5 VDD
0.8 VDD
V
VtL
0.2 VDD
0.5 VDD
V
Continued on next page. No. 4677-8/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Ratings min typ 4.0 max
Parameter Oscillator frequency Oscillator stabilization time Cycle time Input Output
Symbol fCF fCFS
Applicable pins OSC1, OSC2
Conditions Figure 2, 4 MHz
Unit MHz
Note
Ceramic oscillator
Figure 3, 4 MHz 0.9 2.0 0.4 SCK0, SCK1 The timing from Figure 4 and the test load from Figure 5
10
ms s Tcyc s
tCKCY
Serial clock
Low level/ Input high level pulse Output widths Rise/ fall times Output
tCKL
tCKH
1.0
Tcyc
tCKR tCKF tICK SI0, SI1 tCKI Stipulated with respect to the rising edge timing for SCK0 and SCK1 from Figure 4 Stipulated with respect to the rising edge timing for SCK0 and SCK1 from Figure 4 and the test load shown in Figure 5 * Conditions such that the INT0 interrupt is accepted * Conditions such that timer 0 event counter and pulse width measurement inputs are accepted. Figure 6 INT1, INT2 * Conditions such that all interrupts are accepted * Conditions such that timer 1 event counter inputs are accepted. * Conditions such that reset occurs Figure 7 Using a 4 MHz ceramic oscillator Using a 4 MHz external clock Using a 4 MHz ceramic oscillator Using a 4 MHz external clock VDD = 1.8 to 5.5 V 3.0 3.0 1.0 1.0 0.01 0.3 0.3
0.1
s
Data setup time Serial input Data hold time
s s
Serial output
Output delay time
tCKO
SO0, SO1
0.3
s
INT0 high/low level pulse widths
tIOH tIOL
INT0
2
Tcyc
Pulse conditions
High/low level pulse widths for interrupt inputs other than INT0 PIN1 high/low level pulse widths RES high/low level pulse widths
tIIH tIIL
2
Tcyc
tPINH tPINL tRSH tRSL TRS
PIN1
2
Tcyc
RES PD
3 20 5.0 5.0 2.0 2.0 10
Tcyc ms mA 8 mA mA mA A
Comparator response speed
Operating mode current drain
IDD OP
VDD
HALT mode current drain
IDDHALT
VDD
Hold-mode current drain
IDDHOLD
VDD
Note: 1. Common input and output ports with open-drain output specifications are specified for the state with the output n-channel transistor turned off. These pins cannot be used for input when the CMOS output specification option is selected. 2. Common input and output ports with open-drain output specifications are specified for the state with the output n-channel transistor turned off. Ratings for pull-up output specification pins are stipulated for the output pull-up current IPO. These pins cannot be used for input when the CMOS output specification option is selected. 3. Stipulated for CMOS output specifications with the output n-channel transistor in the off state. 4. Stipulated for pull-up output specifications with the output n-channel transistor in the off state. 5. Stipulated for open-drain output specifications with the output n-channel transistor in the off state. 6. In the reset state
No. 4677-9/23
LC66354B, 66356B, 66358B
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Time Table 1 Ceramic Oscillator Guaranteed Constants
C1 = 33 pF 10% 2 MHz (Murata) CSA2.00MG External capacitance type 4 MHz (Murata) CSA4.00MG C2 = 33 pF 10% Rd = 0 C1 = 33 pF 10% C2 = 33 pF 10% Rd = 0 4 MHz (Kyocera) KBR4.0MS 2 MHz (Kyocera) KBR2.0MS C1 = 47 pF 10% C2 = 47 pF 10% Rd = 0 C1 = 33 pF 10% C2 = 33 pF 10% Rd = 0
Figure 4 Serial I/O Timing
No. 4677-10/23
LC66354B, 66356B, 66358B
Figure 5 Timing Load
Figure 6 Input Timing for INT0, INT1, INT2, PIN1 and RES
Figure 7 Comparator Response Speed Trs Timing
No. 4677-11/23
LC66354B, 66356B, 66358B Application Development Tools Programs for the LC66354B, LC66356B and LC66358B microcontrollers are developed on an IBM-PC compatible personal computer running the MS-DOS operating system. A cross assembler and other tools are available. To make application development more convenient, Sanyo also provides a program debugging unit (EVA800/850), an evaluation board (EVA800/850-TB6630X), an evaluation chip (LC66599) and an on-chip EPROM microprocessor (LC66E308).
Structure of the Application Development Tools 1. Program debugging unit (EVA800/850) This is an emulator that provides functions for EPROM writing and serial data communications with external equipment (such as a host computer). It supports application development in machine language and program modification. Its main debugging functions include breaking, stepping and tracing. (The MPM6630X is used for the EVA800/850 monitor ROM.) 2. Evaluation chip board (EVA800/850-TB6630X) The evaluation chip signals and ports are output to the 42-pin connector and when the output cable is connected, the evaluation chip board converts these signals to the same pin assignments as those on the mass production chip. The evaluation chip board includes jumpers for setting options and other states, and these jumper settings allow the evaluation chip to implement the same I/O circuit types and functions as the mass production chip. However, there are differences in the HOLD mode clear timing and the electrical characteristics. Jumper
Type Jumper EXT Jumper setting and mode RC OSC Jumper 1 (J1) External oscillator (external clock) RC oscillator INT (a) Reset method Jumper 2 (J2: RES) Reset by a RUN instruction from the host computer. ON (a) Power supply to the user application board Jumper 3 (J3: VDD) VDD is supplied to the user application printed circuit board through the evaluation chip board.
CF
CF oscillator
Reset by the reset circuit on the user application printed circuit EXT (b) board.
Separate power supplies on the user application printed circuit OFF (b) board and the evaluation chip board.
Switches (SW9, SW10 and SW11)
Type Switch Switch setting and mode ON OFF Port 0 and 1 output levels on reset SW11: P0HL Port 0 high Port 0 low ON OFF SW10: P1HL Port 1 highPort 1 low ON OFF Watchdog timer presence or absence setting SW9: WDC Watchdog timer present Watchdog timer absent
Switches SW1 to SW8: Pull-up resistor option settings * Set the corresponding switch to the on position for built-in pull-up resistors, and set the switch to the off position for open drain output. * These settings can be specified for individual pins.
No. 4677-12/23
LC66354B, 66356B, 66358B 3. Cross Assembler
Cross assembler (file name) Object microprocessors LC66354B, 66356B, 66358B (LC66E308, 66P308) (LC66599) Limitations on program creation SB instruction limitations * LC66354B : Only SB0 can be used. * LC66356B, 66358B : Only SB0 and SB1 can be used. (LC66E308, 66P308) * LC66599 : SB0, SB1, SB2 and SB3 can be used.
LC66S. EXE
4. Simulation chip (See the LC66E308 individual product catalog for more details.) The LC66E308 simulation chip is an on-chip EPROM microprocessor. Mounted configuration operation can be confirmed in the application product by using a dedicated conversion board (the W66EP308D/408D for DIP products and the W66EP308Q/408Q for QFP products) and writing programs with a commercial PROM writer. * Form The LC66E308 has a pin arrangement and functions identical to those of the LC66354B, LC66356B and LC66358B. However, there are differences in the HOLD mode clear timing and the electrical characteristics. The figure below shows the pin assignment. * Options The options (the port 0 and 1 level at reset, the watchdog timer and the port output circuit types) for the microprocessor to be evaluated can be specified by EPROM data. (The next item describes the option data area and definitions.) This allows evaluation with the same peripheral circuits as those that will be used in the mass production product. Pin Assignment
No. 4677-13/23
LC66354B, 66356B, 66358B Option Data Area and Definitions
ROM area Bit 7 6 5 4 2000H 3 2 1 0 7 6 5 2001H 4 3 2 1 0 7 6 5 2002H 4 3 2 1 0 7 6 5 2003H 4 3 2 1 0 7 to 4 3 2004H 2 1 0 2005H 2006H 7 to 0 7 to 0 7 to 4 3 2007H 2 1 0 Unused P1 P0 Level of reset Unused Option item Relation between option and data Must be set to zeros. 1 = ceramic oscillator 0 = external clock Must be set to zero. 1 = high level 0 = low level 1 = present, 0 = absent
Oscillator option
Watchdog timer option P13 P12 P11 P10 P03 P02 P01 P00 Unused P32 P31 P30 P23 P22 P21 P20 P53 P52 P51 P50 P43 P42 P41 P40 Unused P63 P62 P61 P60 Unused Unused Unused PC3 PC2 Unused Output circuit type Output circuit type Output circuit type Output circuit type Output circuit type
1 = PU, 0 = OD
Must be set to zero.
1 = PU, 0 = OD
1 = PU, 0 = OD
1 = PU, 0 = OD
Must be set to zero. Must be set to zero. Must be set to zero. 1 = PU, 0 = OD Must be set to zero.
No. 4677-14/23
LC66354B, 66356B, 66358B LC663XX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification
t2 Bit 11 23 10 22 01 21 00 20
PCh: PCm: PCl: Fn: TIMER0: TIMER1: SIO: P: P (i4): INT: ( ), [ ]: : : : : +: -: --:
Bits 8 to 11 in the PC Bits 4 to 7 in the PC Bits 0 to 3 in the PC User flag, n = 0 to 15 Timer 0 Timer 1 Serial register Port Port indicated by 4 bits of immediate data Interrupt enable flag Indicates the contents of a location Transfer direction, result Exclusive or Logical and Logical or Addition Subtraction Taking the one's complement
No. 4677-15/23
LC66354B, 66356B, 66358B Instructions
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CLA DAA Clear AC Decimal adjust AC in addition Decimal adjust AC in subtraction Clear CF Set CF Complement AC Increment AC Decrement AC Rotate AC right through CF Rotate AC left through CF Transfer AC to E Transfer E to AC Exchange AC with E Increment M Decrement M Increment M direct Decrement M direct Set M data bit Reset M data bit 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0
Number of cycles
Operation AC 0 (Equivalent to LAI0.)
Description
Affected status bits Note
1 2
1 2
Clear AC.
ZF ZF
1
AC (AC) + 6 Add six to AC. (Equivalent to ADI6.) AC (AC) + 10 (Equivalent to ADIOAH.) CF 0 CF 1 AC (AC) AC (AC) + 1 AC (AC) - 1 AC3 (CF), ACn (ACn + 1), CF (AC0) AC0 (CF), ACn + 1 (ACn), CF (AC3) E (AC) AC (E) (AC) (E) M (HL) [M (HL)] +1 M (HL) [M (HL)] -1 M (i8) [M (i8)] + 1 M (i8) [M (i8)] - 1 [M (HL), t2] 1 [M (HL), t2] 0 Add 10 to AC. Clear CF to 0. Set CF to 1. Take the one's complement of AC. Increment AC. Decrement AC. Shift AC (including CF) right.
DAS
2 1 1 1 1 1 1
2 1 1 1 1 1 1
ZF CF CF ZF ZF, CF ZF, CF CF
Accumulator manipulation instructions
CLC STC CMA IA DA RAR
RAL TAE TEA XAE IM DM IMDR i8 DMDR i8 SMB t2 RMB t2
0 0 0 0 0 0
0 1 1 1 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 0 0
0 1 1 1 0 0
0 0 1 0 1 1
1 1 0 0 0 0
1 1 1 1 1 1 2 2 1 1
1 1 1 1 1 1 2 2 1 1
Shift AC (including CF) left. Move the contents of AC to E.
CF, ZF
Move the contents of E to AC. ZF Exchange the contents of AC and E. Increment M (HL). Decrement M (HL). Increment M (i8). Decrement M (i8). Set the bit in M (HL) specified by t0 and t1 to 1. Clear the bit in M (HL) specified by t0 and t1 to 0. ZF ZF, CF ZF, CF ZF, CF ZF, CF
Memory manipulation instruction
1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 0 0 0 0 0 1 0 0
0111 I3 I2 I1 I0 0011 I3 I2 I1 I0 1 1 1 1 t1 t0 t1 t0
AD
Add M to AC
0
0
0
0
0
1
1
0
1
1
Add the contents of AC and M (HL) as two's complement AC (AC) + [M (HL)] values and store the result in AC. AC (AC) + [M (i8)] Add the contents of AC and M (i8) as two's complement values and store the result in AC.
ZF, CF
Arithmetic, logic and comparison instructions
ADDR i8
Add M direct to AC
1100 I7 I6 I5 I4
1001 I3 I2 I1 I0
2
2
ZF, CF
ADC
Add M to AC with CF
0
0
0
0
0
0
1
0
1
1
Add the contents of AC, AC (AC) + [M (HL)] M (HL) and C as two's + (CF) complement values and store the result in AC. AC (AC) + I3, I2, I1, I0 Add the contents of AC and the immediate data as two's complement values and store the result in AC.
ZF, CF
ADI i4
Add immediate data to AC
1 0
1 0
0 1
0 0
1111 I3 I2 I1 I0
2
2
ZF
SUBC
Subtract AC from M with CF And M with AC then store AC
0
0
0
1
0
1
1
1
1
1
Subtract the contents of AC AC [M (HL)] - (AC) and CF from M (HL) as two's - (CF) complement values and store the result in AC. AC (AC) [M (HL)] Take the logical and of AC and M (HL) and store the result in AC.
ZF, CF
2
ANDA
0
0
0
0
0
1
1
1
1
1
ZF
Note: 1. Has a vertical skip function. 2. CF will be zero if there was a borrow and one otherwise.
Continued on next page. No. 4677-16/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 ORA Or M with AC then store AC Exclusive or M with AC then store AC And M with AC then store M Or M with AC then store M 0 0 0 0 0 1 0 1
Number of cycles
Operation
Description
Affected status bits Note
1
1
AC (AC) [M (HL)] AC (AC) [M (HL)] M (HL) (AC) [M (HL)] M (HL) (AC) [M (HL)]
Take the logical or of AC and M (HL) and store the result ZF in AC. Take the logical exclusive or of AC and M (HL) and store the result in AC. Take the logical and of AC and M (HL) and store the result in M (HL). ZF
EXL
0
0
0
1
0
1
0
1
1
1
ANDM
0
0
0
0
0
0
1
1
1
1
ZF
ORM
0
0
0
0
0
1
0
0
1
1
Take the logical or of AC and M (HL) and store the result ZF in M (HL). Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result.
Arithmetic, logic and comparison instructions
CM
Compare AC with M
0
0
0
1
0
1
1
0
1
1
[M (HL)] + (AC) + 1
Magnitude comparison [M (HL)] > (AC) [M (HL)] = (AC) [M (HL)] < (AC)
CF ZF 0 1 1 0 1 0
ZF, CF
Compare the contents of AC and the immediate data I3 I2 I1 I0 and set or clear CF and ZF according to the result. CI i4 Compare AC wiht immediate data 1 1 1 0 0 1 0 0 1111 I3 I2 I1 I0 2 2 I3 I2 I1 I0 + (AC) +1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC ZF 1 if (DPL) = I3 I2 I1 I0 ZF 0 if (DPL) = I3 I2 I1 I0 ZF 1 if (AC, t2) = [M (HL), t2] ZF 0 if (AC, t2) = [M (HL), t2] AC M (HL) E M (HL +1) AC I3 I2 I1 I0 AC [M (i8)] M (HL) (AC) M (HL) (AC) M (HL + 1) (E) CF ZF 0 1 1 0 1 0 ZF, CF
CLI i4
Compare DPL with immediate data
1 1
1 0
0 1
0 1
1111 I3 I2 I1 I0
2
2
Compare the contents of DPL with the immediate data. Set ZF ZF if identical and clear ZF if not. Compare the corresponding bits specified by t0 and t1 in AC and M(HL). Set ZF if identical and clear ZF if not. Load the contents of M2 (HL) into AC, E. Load the immediate data into AC. Load the contents of M (i8) into AC. Store the contents of AC into M (HL). Store the contents of AC, E into M2(HL). Load the contents of M (reg) into AC. The reg is either HL or XY depending on t0. ZF ZF 3
CMB t2
Compare AC bit with M data bit
1 1
1 1
0 0
0 1
1 0
1 0
11 t1 t0
2
2
ZF
LAE LAI i4
Load and store instructions
Load AC and E from M2 (HL) Load AC with immediate data Load AC from M direct Store AC to M Store AC and E to M2 (HL)
0 1
1 0
0 0
1 0
1
1
0
0
1 1 2 1 1
1 1 2 1 1
I3 I2 I1 I0 0001 I3 I2 I1 I0 0 1 1 1 1 1 1 0
LADR i8 S SAE
1100 I7 I6 I5 I4 0 0 1 1 0 0 0 1
LA reg
Load AC from M (reg)
0
1
0
0
1
0
t0
0
1
1
AC [M (reg)]
reg HL XY
t0 0 1
ZF
Note: 3. Has a vertical skip function.
Continued on next page. No. 4677-17/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
Number of cycles
Operation
Description
Affected status bits Note
LA reg, I
Load AC from M (reg) then increment reg
0
1
0
0
1
0
t0
1
1
2
AC [M (reg)] DPL (DPL) + 1 or DPY (DPY) + 1
Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. Exchange the contents of M (reg) and AC. The reg is either HL or XY depending on t0. reg HL XY t0 0 1
4
LA reg, D
Load AC from M (reg) then decrement reg
0
1
0
1
1
0
t0
1
1
2
AC [M (reg)] DPL (DPL) - 1 or DPY (DPY) - 1
5
XA reg
Exchange AC with M (reg)
0
1
0
0
1
1
t0
0
1
1
(AC) [M (reg)]
Load and store instructions
XA reg, I
Exchange AC with M (reg) then increment reg
0
1
0
0
1
1
t0
1
1
2
(AC) [M (reg)] DPL (DPL) + 1 or DPY (DPY) + 1
Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. The relationship between t0 and reg is the as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. The relationship between t0 and reg is the as that for the XA reg instruction. Exchange the contents of AC with M (i8). Load the immediate data i8 into E, AC. Load into E, AC the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. Output from ports 4 and 5 the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC.
ZF
6
XA reg, D
Exchange AC with M (reg) then decrement reg
0
1
0
1
1
1
t0
1
1
2
(AC) [M (reg)] DPL (DPL) - 1 or DPY (DPY) - 1
ZF
7
XADR i8 LEAI i8
Exchange AC with M direct Load E & AC with immediate data Read table data from program ROM
1100 I7 I6 I5 I4 1100 I7 I6 I5 I4
1000 I3 I2 I1 I0 0110 I3 I2 I1 I0
2 2
2 2
(AC) [M (i8)] E I7 I6 I5 I4 AC I3 I2 I1 I0 E, AC [ROM (PCh, E, AC)]
RTBL
0
1
0
1
1
0
1
0
1
2
RTBLP
Read table data from program ROM then output to P4, 5
0
1
0
1
1
0
0
0
1
2
Port 4, 5 [ROM (PCh, E, AC)]
Note: 4. 5. 6. 7.
ZF is set according to the result of incrementing DPL or DPY. ZF is set according to the result of decrementing DPL or DPY. ZF is set according to the result of incrementing DPL or DPY. ZF is set according to the result of decrementing DPL or DPY.
Continued on next page. No. 4677-18/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Load DPH with zero and DPL with immediate data respectively Load DPH with immediate data Load DPL with immediate data Load DPH, DPL with immediate data Load DPX, DPY with immediate data Increment DPL Decrement DPL Increment DPY Decrement DPY Transfer AC to DPH Transfer DPH to AC Exchange AC with DPH Transfer AC to DPL Transfer DPL to AC Exchange AC with DPL Transfer AC to DPX Transfer DPX to AC Exchange AC with DPX Transfer AC to DPY Transfer DPY to AC Exchange AC with DPY
Number of cycles
Operation
Description
Affected status bits Note
LDZ i4
0
1
1
0
I3 I2 I1 I0 1111 I3 I2 I1 I0 1111 I3 I2 I1 I0 0000 I3 I2 I1 I0 0010 I3 I2 I1 I0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1
1
1
DPH 0 DPL I3 I2 I1 I0 DPH I3 I2 I1 I0 DPL I3 I2 I1 I0 DPH I7 I6 I5 I4 DPL I3 I2 I1 I0 DPX I7 I6 I5 I4 DPY I3 I2 I1 I0 DPL (DPL) + 1 DPL (DPL) - 1 DPY (DPY) + 1 DPY (DPY) - 1 DPH (AC) AC (DPH) (AC) (DPH) DPL (AC) AC (DPL) (AC) (DPL) DPX (AC) AC (DPX) (AC) (DPX) DPY (AC) AC (DPY) (AC) (DPY)
Load zero into DPH and the immediate data i4 into DPL. Load the immediate data i4 into DPH. Load the immediate data i4 into DPL. Load the immediate data into DLH, DPL. Load the immediate data into DLX, DPY. Increment the contents . of DPL Decrement the contents of DPL. Increment the contents of DPY. Decrement the contents of DPY. Transfer the contents of AC to DPH. Transfer the contents of DPH . ZF to AC Exchange the contents of AC and DPH. Transfer the contents of AC to DPL. Transfer the contents of DPL to AC. Exchange the contents of AC and DPL. Transfer the contents of AC to DPX. Transfer the contents of DPX to AC. Exchange the contents of AC and DPX. Transfer the contents of AC to DPY. Transfer the contents of DPY to AC. Exchange the contents of AC and DPY Set the flag specified by n4 to 1. ZF ZF ZF ZF ZF ZF ZF
LHI i4 LLI i4
1 0 1 0
1 0 1 0
0 0 0 0
0 0 0 1
2 2
2 2
LHLI i8
1100 I7 I6 I5 I4 1100 I7 I6 I5 I4 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0
2
2
LXYI i8
2
2
IL DL
Data pointer manipulation instructions
1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1
1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1
IY DY TAH THA XAH TAL TLA XAL TAX TXA XAX TAY TYA XAY
Flag manipulation instructions
SFB n4
Set flag bit
0
1
1
1
n 3 n2 n1 n0
1
1
Fn 1
RFB n4
Reset flag bit
0
0
1
1
n 3 n2 n1 n0
1
1
Fn 0
Clear the flag specified by n4 to 0.
ZF
Continued on next page. No. 4677-19/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 JMP addr Jump in the current bank Jump to the address stored at E and AC in the current page 1 1 1 0 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Number of cycles
Operation PC12 PC12 PC11 to 0 P11 to P0 PC12 to PC8 PC12 to PC8 PC7 to 4 (E) PC3 to 0 (AC) PC12, 11 0 PC10 to 0 P10 to P0 M4 (SP) (CF, ZF, PC12 to 0) SP (SP) - 4 PC12 to 6, PC1 to 0 0 PC5 to 2 P3 to P0 M4 (SP) (CF, ZF, PC12 to 0) SP SP - 4
Description Jump to the location in the same bank specified by the immediate data P12. Jump to the location determined by replacing the lower 8 bits of the PC by E, AC.
Affected status bits Note
2
2
8
JPEA
0
0
1
0
0
1
1
1
1
1
CAL addr
Call subroutine
0101 P7 P6 P5 P4
0 P10 P9 P8 P3 P2 P1 P0
2
2
Call a subroutine.
Jump and subroutine instructions
CZP addr
Call subroutine in the zero page
1
0
1
0
P3 P2 P1 P0
1
2
Call a subroutine on page 0 in bank 0.
BANK
Change bank
0
0
0
1
1
0
1
1
1
1
Change the memory bank and register bank. Store the contents of reg in M2 (SP). Subtract 2 from SP after the store.
PUSH reg
Push reg on M2 (SP)
1 1
1 1
0 1
0 1
1 1
1 i1
1 i0
1 0
2
2
M2 (SP) (reg) SP (SP) - 2
reg HL XY AE Illegal setting
i1 0 0 1 1
i0 0 1 0 1
POP reg
Pop reg off M2 (SP)
1 1
1 1
0 1
0 0
1 1
1 i1
1 i0
1 0
2
2
SP (SP) + 2 reg [M2 (SP)]
Add 2 to SP and then load the contents of M2 (SP) into reg. The relation between i1 i0 and reg is the same as that for the PUSH reg instruction. Return from a subroutine or interrupt handling routine. ZF and CF are not restored. Return from a subroutine or interrupt handling routine. ZF and CF are restored. Branch to the location in the same page specified by P0 to P7 if the bit in AC specified by the immediate data t1 t0 is one. Branch to the location in the same page specified by P0 to P7 if the bit in AC specified by the immediate data t1 t0 is zero. Branch to the location in the same page specified by P0 to P7 if the bit in M (HL) specified by the immediate data t1 t0 is one. Branch to the location in the same page specified by P0 to P7 if the bit in M (HL) specified by the immediate data t1 t0 is zero. ZF, CF
RT
Return from subroutine Return from interrupt routine
0
0
0
1
1
1
0
0
1
2
SP (SP) + 4 PC [M4 (SP)] SP (SP) + 4 PC [M4 (SP)] CF, ZF [M4 (SP)] PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if (AC, t2) =1 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if (AC, t2) =0 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if [M (HL), t2] = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if [M (HL), t2] = 0
RTI
0
0
0
1
1
1
0
1
1
2
BAt2 addr
Branch on AC bit
1101 P7 P6 P5 P4
0 0 t1 t0 P3 P2 P1 P0
2
2
Branch instructions
MNAt2 addr
Branch on no AC bit
1001 P7 P6 P5 P4
0 0 t1 t0 P3 P2 P1 P0
2
2
BMt2 addr Branch on M bit
1101 P7 P6 P5 P4
0 1 t1 t0 P3 P2 P1 P0
2
2
BNMt2 addr
Branch on no M bit
1001 P7 P6 P5 P4
0 1 t1 t0 P3 P2 P1 P0
2
2
Note: 8. This becomes PC12 + (PC12) immediately following a BANK instruction.
Continued on next page. No. 4677-20/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
Number of cycles
Operation PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if [P (DPL), t2] =1 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if [P (DPL), t2] =0
Description
Affected status bits Note
BPt2 addr
Branch on port bit
1101 P7 P6 P5 P4
1 0 t1 t0 P3 P2 P1 P0
2
2
Branch to the location in the same page specified by P0 to P7 if the bit in port (DPL) specified by the immediate data t1 t0 is one. Branch to the location in the same page specified by P0 to P7 if the bit in port (DPL) specified by the immediate data t1 t0 is zero.
9
BNPt2 addr
Branch on no port bit
1001 P7 P6 P5 P4
1 0 t1 t0 P3 P2 P1 P0
2
2
9
BC addr
Branch on CF
1101 P7 P6 P5 P4
1100 P3 P2 P1 P0
2
2
PC7 to 0 P7 P6 P5 P4 P3 P2 Branch to the location in the P 1 P0 same page specified by P0 to if (CF) P7 if CF is one. =1 PC7 to 0 P7 P6 P5 P4 P3 P2 Branch to the location in the P 1 P0 same page specified by P0 to if (CF) P7 if CF is zero. =0 PC7 to 0 P7 P6 P5 P4 P3 P2 Branch to the location in the P 1 P0 same page specified by P0 to if (ZF) P7 if ZF is one. =1 PC7 to 0 P7 P6 P5 P4 P3 P2 Branch to the location in the P 1 P0 same page specified by P0 to if (ZF) P7 if ZF is zero. =0 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if (Fn) =1 PC7 to 0 P7 P6 P5 P4 P3 P2 P 1 P0 if (Fn) =0 AC (P0) AC [P (DPL)] M (HL) [P (DPL)] AC [P (i4)] E [P (4)] AC [P (5)] P (DPL) (AC) P (DPL) [M (HL)] P (i4) (AC) P (4) (E) P (5) (AC) Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is one. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is zero. Input the contents of port 0 to AC. Input the contents of port P (DPL) to AC. Input the contents of port P (DPL) to M (HL). Input the contents of P (i4) to AC. Input the contents of ports P (4) and P (5) to E and AC respectively. Output the contents of AC to port P (DPL). Output the contents of M (HL) to port P (DPL). Output the contents of AC to P (i4). Output the contents of E and AC to ports P (4) and P (5) respectively. ZF ZF ZF
Branch instructions
BNC addr
Branch on no CF
1001 P7 P6 P5 P4
1100 P3 P2 P1 P0
2
2
BZ addr
Branch on ZF
1101 P7 P6 P5 P4
1101 P3 P2 P1 P0
2
2
BNZ addr
Branch on no ZF
1001 P7 P6 P5 P4
1101 P3 P2 P1 P0
2
2
BFn4 addr Branch on flag bit
1111 P7 P6 P5 P4
n 3 n2 n1 n0 P3 P2 P1 P0
2
2
BNFn4 addr
Branch on no flag bit
1011 P7 P6 P5 P4
n3 n2 n1 n0 P3 P2 P1 P0
2
2
IP0 IP IPM IPDR i4
I/O instructions
Input port 0 to AC Input port to AC Input port to M Input port to AC direct Input port 4, 5 to E, AC respectively Output AC to port Output M to port Output AC to port direct Output E, AC to port 4, 5 respectively
0 0 0 1 0 1 1 0 0 1 0 1 1
0 0 0 1 1 1 1 0 0 1 1 1 1
1 1 0 0 1 0 0 1 0 0 1 0 0
0 0 1 0 0 0 1 0 1 0 1 0 1
0 0 1
0 1 0
0 1 0
0 0 1
1 1 1 2
1 1 1 2
1111 I3 I2 I1 I0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0
IP45
2
2
OP OPM OPDR i4
1 1 2
1 1 2
1111 I3 I2 I1 I0 1 0 1 1 1 0 1 1
OP45
2
2
Note: 9. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out.
Continued on next page. No. 4677-21/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SPB t2 Set port bit 0 0 0 0 1 0 t1 t0
Number of cycles
Operation
Description Set to one the bit in port P (DPL) specified by the immediate data t1 t0. Clear to zero the bit in port P (DPL) specified by the immediate data t1 t0. Take the logical and of P (P3 to P0) and the immediate data I3 I2 I1 I0 and output the result to P (P3 to P0).
Affected status bits Note
1
1
[P (DPL), t2] 1
I/O instructions
RPB t2
Reset port bit
0
0
1
0
1
0
t1 t0
1
1
[P (DPL), t2] 0
ZF
ANDPDR i4, p4
And port with immediate data then output Or port with immediate data then output
1100 I3 I2 I1 I0
0101 P3 P2 P1 P0
2
2
P (P3 to P0) [P (P3 to 0)] I3 to 0
ZF
ORPDR i4, p4
1100 I3 I2 I1 I0
0100 P3 P2 P1 P0
2
2
P (P3 to P0) [P (P3 to 0)] I3 to 0
Take the logical or of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0).
WTTM0
Write timer 0
1
1
0
0
1
0
1
0
1
2
Write the contents of M2 (HL), TIMER0 [M2 (HL)], AC into the timer 0 reload (AC) register. Write the contents of E, AC TIMER1 (E), (AC) into the timer 1 reload register A. M2 (HL), AC (TIMER0) E, AC (TIMER1) Start timer 0 counter Start timer 1 counter Stop timer 0 counter Stop timer 1 counter MSE 1 MSE 0 EDIH (EDIH) EDIL (EDIL) EDIH (EDIL) EDIL (EDIL) SP (E), (AC) E, AC (SP) i4 i4 i4 i4 Read out the contents of the timer 0 counter into M2 (HL), AC. Read out the contents of the timer 1 counter into E, AC. Start the timer 0 counter. Start the timer 1 counter. Stop the timer 0 counter. Stop the timer 1 counter. Set the interrupt master enable flag to one. Clear the interrupt master enable flag to zero. Set the interrupt enable flag to one. Set the interrupt enable flag to one. Clear the interrupt enable flag to zero. Clear the interrupt enable flag to zero. Transfer the contents of E, AC to SP. Transfer the contents of SP to E, AC. Enter halt mode. ZF ZF
WTTM1
Timer control instructions
Write timer 1
1 1
1 1
0 1
0 1
1 0
1 1
1 0
1 0
2
2
RTIM0
Read timer 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 1 1 1 1 1 1 1 1 1 1 0 1 0
1 1 0 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 0 1 1 1 0 1 1 1 0 1 0
1
2
RTIM1 START0 START1 STOP1 STOP1 MSET MRESET
Read timer1 Start timer 0 Start timer 1 Stop timer 0 Stop timer 1 Set interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt low Disable interrupt high Disable interrupt low Write SP Read SP
2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2
Interrupt control instructions
EIH i4 EIL i4 DIH i4 DIL i4 WTSP RSP
1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1101 I3 I2 I1 I0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1
Standby control instructions
HALT
HALT
2
2
HALT
HOLD
HOLD
2
2
HOLD
Enter HOLD mode.
Continued on next page. No. 4677-22/23
LC66354B, 66356B, 66358B
Continued from preceding page.
Instruction group Number of bytes
Instruction code Mnemonic D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 STARTS WTSIO RSIO Start serial IO Write serial IO Read serial IO 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 0
Number of cycles
Operation
Description
Affected status bits Note
Serial I/O control instructions
2 2 2
2 2 2
START SI O SIO (E), (AC) E, AC (SIO)
Start SIO operation. Write the contents of E, AC to SIO. Read the contents of SIO into E, AC. Consume one machine cycle without performing any operation. Specify the memory bank.
Other instructions
NOP
No operation
1
1
No operation PC12 I1 I0
SB i2
Select bank
11 I1 I0
2
2
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1998. Specifications and information herein are subject to change without notice. PS No. 4677-23/23

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